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sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 1 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 2.8 v to 5.5 v input 5 a synchronous buck regulator description the sip12108 is a high frequency current-mode constant on-time (cm-cot) synchronous buck regulator with integrated high-side and lo w-side power mosfets. its power stage is capable of supplying 5 a continuous current at 4 mhz switching frequency. this regulator produces an adjustable output voltage down to 0.6 v from 2.8 v to 5.5 v input rail to accommodate a variety of applications, including computing, consumer electronics, telecom, and industrial. sip12108s cm-cot architecture delivers ultra-fast transient response with mini mum output capacitance and tight ripple regulation at very light load. the part is stable with any capacitor type and no esr network is required for loop stability. the device al so incorporates a power saving scheme that significantly increases light load efficiency. the sip12108 integrates a full protection feature set, including output overvoltage protection (ovp), output under voltage protection (uvp) and th ermal shutdown (otp). the a version of the device, sip12108a, does not have the uvp feature. they also incorpo rate uvlo for the input rail and an internal soft-start ramp. the sip12108 is available in lead (pb)-free power enhanced 3 mm x 3 mm qfn-16 package. features ? 2.8 v to 5.5 v input voltage ? adjustable output voltage down to 0.6 v ? 5 a continuous output current ? programmable switching frequency up to 4 mhz ? 95 % peak efficiency ? stable with any capacitor. no external esr network required. ? ultrafast transient response ? selectable power saving (psm) mode or forced continuous mode ? 1 % accuracy of v out setting ? pulse-by-pulse current limit ? scalable with sip12107 - 3 a ? sip12108 is fully protected with otp, scp, uvp, ovp ? sip12108a is fully protected with otp, scp, ovp ? pgood indicator ? powercad simulation software available at ? vishay.transim.com/login.aspx ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ? point of load regulation for low-power processors, network processors, dsps, fpgas, and asics ? low voltage, distributed power architectures with 3.3 v or 5 v rails ? computing, broadband, networking, lan/wan, optical, test and measurement ? a/v, high density cards, storage, dsl, stb, dvr, dtv, industrial pc typical application circuit fig. 1 - typical application circuit for sip12108 v in p g ood en av in lx input = 2.8 v to 5.5 v p g nd a g nd power g ood enable v out v out v fb g mo r on auto power s ave mode
sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 2 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 stresses beyond those listed under absolute maximum ratings ma y cause permanent damage to th e device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those in dicated in the operational sectio ns of the specifications is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. absolute maximum ratings electrical parameter conditions limit unit v in reference to p gnd -0.3 to 6 v av in reference to a gnd -0.3 to 6 lx reference to p gnd -0.3 to 6 a gnd to p gnd -0.3 to +0.3 all logic inputs reference to a gnd -0.3 to av in + 0.3 temperature max. operating junction temperature 150 c storage temperature -65 to 150 power dissipation junction to ambien t thermal impedance (r thja ) 36.3 c/w maximum power dissipation ambient temperature = 25 c 3.4 w ambient temperature = 100 c 1.3 esd protection hbm 4 kv recommended operating range electrical parameter mi nimum typical maximum unit v in 2.8 - 5.5 v av in 2.8 - 5.5 lx -1 - 5.5 v out 0.6 - 0.85 x v in ambient temperature -40 to 85 c
sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 3 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical specifications parameter symbol test condition unless otherwise specified v in = av in = 3.3 v, t a = -40 c to 85 c limits unit min. typ. max. power supply power input voltage range v in 2.8 - 5.5 v bias input voltage range av in 2.8 - 5.5 input current i in_noload non- switching, i o = 0 a, r on = 100 k ? , auto = low - 1200 - a shutdown current i in_shdn en = 0 v - 6 9.5 av in uvlo threshold av in_uvlo av in rising 2.3 2.55 2.8 v av in uvlo hysteresis av in_uvlo_hys - 300 - mv pwm controller feedback reference v fb t a = 0 c to +70 c 0.594 0.600 0.606 v t a = -40 c to +85 c 0.591 0.600 0.609 v fb input bias current i fb - 2 200 na transconductance g m -1-ms gmo source current i gmo_source -50- a gmo sink current i gmo_sink -50- switching frequency range f sw guaranted by design 0.2 - 4 mhz minimum on-time t on_min guaranted by design - 50 - ns minimum off-time t off_min v out = 1.2 v, r on = 100 k ? - 125 - soft start time t ss -1.5-ms integrated mosfets high-side on resistance r on_hs v in = av in = 5 v -3551 m ? low-side on resistance r on_ls -2335 fault protections over current limit i ocp inductor valley current - 7.5 - a output ovp threshold v fb_ovp v fb with respect to 0.6 v reference -21- % output uvp threshold v fb_uvp --25- over temperature protection rising temperature - 160 - c hysteresis - 30 - power good power good output threshold v fb_rising_vth_ov v fb rising above 0.6 v reference - 21 - % v fb_falling_vth_uv v fb falling below 0.6 v reference - -12.5 - power good on resistance r on_pgood -3060 ? power good delay time t dly_pgood -4-s enable threshold logic high level v en_h 1.5 - - v logic low level v en_l --0.4
sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 4 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 functional block diagram fig. 2 - sip12108 functi onal block diagram note (1) output undervoltage protection (uvp) disabled ordering information part number package marking (line 2: p/n) sip12108dmp-t1ge4 qfn16 3x3 2108 sip12108admp-t1ge4 (1) qfn16 3x3 108a SIP12108DB n/a sip12108adb (1) on-time g enerator + - pwm comparator s oft s tart 0.6 v reference a g nd p g ood av in en v fb v in 1,16 v in lx p g nd v in v in 11,12,13 14,15 anti-xcond control 8 6 2 3 zcd + - 0.72 v ov comparator control lo g ic s ection ocp uvlo otp 5 auto 7 g mo ota + - + i s en s e 9 i-v converter i s en s e r on v out 4 10 + - 0.45 v v fb uv comparator ( s ip12108 only) pad current mirror format: line 1: dot line 2: p/n line 3: s iliconix logo + e s d s ymbol line 4: factory code + year code + work week code + lot code p/n fywll
sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 5 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pin configuration fig. 3 - sip12108 pin configuration (top view) ? ? pin configuration pin number name function 1, 16 v in input supply voltage for power mos. v in = 2.8 v to 5.5 v 2av in input supply voltage for internal circuitry. av in = 2.8 v to 5.5 v 3 en enable pin. pull enable above 1.5 v to enable the pa rt and below 0.4 v to disabl e. do not float this pin. 4r on an external resistor between r on and gnd sets the switching on time. 5auto sets switching mode. connect auto to av in for forced continuo us mode and auto to gnd for power save mode. do not float. 6 pgood power good output. open drain. 7 gmo connect to an external rc network for loop comp ensation and droop function 8a gnd analog ground 9v fb feedback voltage. 0.6 v (typ.). use a resistor divider between v out and a gnd to set the output voltage. 10 v out v out , output voltage sense connection 11, 12, 13 lx switching output, inductor connection point 14, 15 p gnd power ground ep exposed paddle (bottom). connect to a good pcb thermal ground plane. lx r on en av in v in v fb v out lx lx auto g mo p g ood a g nd v in p g nd p g nd 1 2 3 4 5 6 7 8 12 11 10 9 15 14 13 16 qfn16 3 x 3
sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 6 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics (v in = 3.3 v, l = 1 h, c = 3 x 22 f, f sw = 1.2 mhz unless noted otherwise) fig. 4 - efficiency - pwm mode fig. 5 - load regulation - pwm mode fig. 6 - f sw variation - pwm mode fig. 7 - efficiency - psm mode fig. 8 - load regulation - psm mode fig. 9 - f sw variation - psm mode 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 efficiency (%) i out (a) vo -1.2v vo- 1.8v -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 0.12 0.01 0.1 1 10 load regulation (%) i out (a) vo - 1.2v vo - 1.8v 0 0.2 0.4 0.6 0.8 1 1.2 0.01 0.1 1 10 fsw (mhz) i out (a) vo - 1.2v vo - 1.8v 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 efficiency (%) i out (a) vo - 1.2v vo - 1.8v -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 0.12 0.01 0.1 1 10 load regulation (%) i out (a) vo - 1.2v vo - 1.8v 0 0.2 0.4 0.6 0.8 1 1.2 0.01 0.1 1 10 fsw (mhz) i out (a) vo - 1.2v vo - 1.8v
sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 7 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics (v in = 3.3 v, l = 1 h, c = 3 x 22 f, f sw = 1.2 mhz unless noted otherwise) fig. 10 - pwm mode- steady - state ripple and lx, 5 a load ch1 = v out , 20 mv/div, ch2 = lx, 2 v/div, time = 1 s/div fig. 11 - psm mode- steady - state ripple and lx, 0 a load ch1 = v out , 20 mv/div, ch2 = lx, 2 v/div, time = 10 ms/div fig. 12 - load step 0 a to 5 a to 0 a ch1 = i load , ch2 = v out , 500 mv/div, ch4 = i coil , 5 a/div, time = 100 s/div fig. 13 - pwm mode- steady - state ripple and lx, 0 a load ch1 = v out , 20 mv/div, ch2 = lx, 2 v/div, time = 1 s/div fig. 14 - psm mode- steady - state ripple and lx, 0 a load ch1 = v out , 20 mv/div, ch2 = lx, 2 v/div, time = 1 s/div fig. 15 - load step 0 a to 5 a, rising edge ch1 = i load , ch2 = v out , 200 mv/div, ch4 = i coil , 5 a/div, time = 20 s/div ch1 ch2 ch1 ch2 ch1 ch2 ch4 ch1 ch2 ch1 ch2 ch1 ch2 ch4
sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 8 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics (v in = 3.3 v, l = 1 h, c = 3 x 22 f, f sw = 1.2 mhz unless noted otherwise) fig. 16 - load step 0 a to 5 a, falling edge ch1 = i load , ch2 = v out , 200 mv/div, ch4 = i coil , 5 a/div, time = 20 s/div fig. 17 - turn-off time psm mode, 0 a load ch1 = v out , 500 mv/div, ch2 = en, 2 v/div, ch3 = pgood, 5 v/div, ch4 = i coil , 2 a/div, time = 500 s/div fig. 18 - turn-off time pwm mode, 5 a load ch1 = v out , 500 mv/div, ch2 = en, 2 v/div, ch3 = pgood, 5 v/div, ch4 = i coil , 2 a/div, time = 500 s/div fig. 19 - turn-on time psm mode, 0 a load ch1 = v out , 500 mv/div, ch2 = en, 2 v/div, ch3 = pgood, 5 v/div, ch4 = i coil , 2 a/div, time = 500 s/div fig. 20 - turn-on time pwm mode, 5 a load ch1 = v out , 500 mv/div, ch2 = en, 2 v/div, ch3 = pgood, 5 v/div, ch4 = i coil , 2 a/div, time = 500 s/div ch1 ch2 ch4 ch2 ch1 ch4 ch3 ch2 ch1 ch4 ch3 ch2 ch1 ch4 ch3 ch2 ch1 ch4 ch3
sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 9 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 operational description device overview sip12108 is a high-efficiency monolithic synchronous buck regulator capable of delivering up to 5 a continuous current. the device has progr ammable switching frequency up to 4 mhz. the control scheme is based on current-mode constant-on-time architecture, which delivers fast transient response and minimi zes external compone nts. thanks to the internal current ramp inform ation, no high-esr output bulk or virtual esr network is re quired for the loop stability. this device also incorporates a power saving feature by enabling diode emulation mode and frequency foldback as load decreases. sip12108 has a full set of protection and monitoring features: - over current protection in pulse-by-pulse mode - output over voltage protection - output under voltage prote ction with device latch - over temperature prote ction with hysteresis - dedicated enable pin for easy power sequencing - power good open drain output this device is available in qfn16 3x3 package to deliver high power density an d minimize pcb area. power stage sip12108 integrated synchronous mosfets . the mosfets are optimized to achieve 95 % efficiency at 2 mhz switching frequency. the power input voltage (v in ) can go up to 5.5 v and as low as 2.8 v for power conversion . the logic bias voltage (av in ) ranges from 2.8 v to 5.5 v. pwm control mechanism sip12108 employs a state-of-the-art current-mode cot control mechanism. during stea dy-state operation, output voltage is compared with intern al reference (0.6 v typ.) and the amplified error signal (v comp ) is generated on the comp pin. in the meantime, inductor valley current is sensed, and its slope (i sense ) is converted into a voltage signal (v current ) to be compared with v comp . once v current is lower than v comp , a single shot on-time is generated for a fixed time programmed by the external r on . figure 4 illustrates the basic block diagram for cm-cot architecture and figure 5 demonstrates the basic operational principle: ? ? ? fig. 21 - cm-cot block diagram h g l g h g l g ota - + bandgap v ref v out current mirror l s fet pwm comparator - + - + v in i-amp on-time g enerator v out v in r on control logic & mo s fet driver v comp i s en s e v current r1 r2
sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 10 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 22 - cm-cot operational principle the following equation illustra tes the relationship between on-time, v in , v out and r on value: ? ? once on-time is set, the pseudo constant frequency is then determined by the following equation: loop stability and compensator design due to the nature of current mode cont rol, a simple rc network (type ii compens ator) is required between comp and a gnd for loop stability and transient respon se purposes. the general concept of this loop design is to in troduce a single zero through t he compensator to determine the crossover frequency of overall close loop system. the overall loop can be broken down into following segments. output feedback divider transfer function h fb : voltage compensator transfer function g comp (s): modulator transfer function h mod (s): the complete loop transfer function is given by: when: c comp = compensation capacitor r comp = compensation resistor gm = error amplifier transconductance r load = load resistance c o = output capacitor r ds(on) = ls switch resistance r fb1 = feedback resistor connect to lx r fb2 = feedback resistor connect to ground r o = output impedance of error amplifier = 20 m ? av 1 = voltage to current gain = 3 v current v comp pwm fixed on-time v out v in t on = r on x k x , where k = 10.45 x 10 -12 a con s tant s et internally s w = = = d t on 1 v out v in v out v in x r on x k r on x k h fb r fb2 r fb1 x r fb2 ----------------------------- - = g comp (s) r o x 1 + sc comp r comp ?? 1 + sr o c comp ?? ------------------------------------------------------------------------- gm = h mod (s) 1 av 1 x r ds(on) ----------------------------------- x r load x 1 + sc o r esr ?? 1 + sc o r load ?? ------------------------------------------------------------- - = h mod (s) r fb2 r fb1 x r fb2 ----------------------------- - x r o x 1 + sc comp r comp ?? 1 + sr o c comp ?? ------------------------------------------------------------------------- gm x 1 av 1 x r ds(on) ----------------------------------- x r load x 1 + sc o r esr ?? 1 + sc o r load ?? ------------------------------------------------------------- - =
sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 11 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 power save mode using auto pin to further improve efficiency at light loads, sip12108 provides a set of innovative i mplementations to eliminate ls recirculating current and switching losses. the internal zero crossing detector (zcd) monitors lx node voltage to determine when inductor current starts to flow negatively. in power saving mode (psm), as soon as inductor valley current crosses zero, the de vice first deploys diode emulation mode by turning of f ls fet. if load further decreases, switching freq uency is further reduced proportional to load condition to save switching losses. the switching frequency is set by the controller to maintain regulation. at zero load this frequency can go as low as hundreds of hz. whenever fixed frequency pwm operation is required over the entire load span, the power saving mode feature can be disabled by connecting auto pin to v in or av in . output monitoring and protection features output over-current protection (ocp) sip12108 has pulse-by-pulse over-current limit control. the inductor valley current is mo nitored during ls fet turn-on period through r ds(on) sensing. after a pre-defined time, the valley current is compared with internal threshold (7.5 a typ.) to determine the threshold for ocp. if monitored current is higher than threshold, hs tu rn-on pulse is skipped and ls fet is kept on until the valley current returns below ocp limit. in the severe over-current cond ition, pulse-by-pulse current limit eventually triggers ou tput under-voltage protection (uvp), which latches the device off to prevent catastrophic thermal-related failure. uvp is described in the next section. ocp is enabled immediately after av in passes uvlo level. figure 6 illustrates the ocp operation. fig. 23 - over-current protection illustration output under-voltag e protection (uvp) uvp is implemented by moni toring output through v fb pin. once the voltage level at v fb is below 0.45 v for more than 20 s, then uvp event is recognized and both hs and ls mosfets are turned off. uvp latches the device off until either av in or en is recycled. uvp is only active after the completion of soft-start sequence. this function only exists on sip12108. on the a version of the device, sip12108a, this feature is disabled. output over-voltage protection (ovp) for ovp implementation, outp ut is monitored through v fb pin. after soft-start, if the voltage level at v fb is above 21 % (typ.), ovp is triggered with hs fet turning off and ls fet turning on immediately to discharge the output. normal operation is resumed once v fb drops back to 0.6 v. ovp is active immediately after av in passes uvlo level. ? ? ? over-temperature protection (otp) sip12108 has internal thermal monitor block that turns off both hs and ls fets when j unction temperature is above 160 c (typ.). a hysteresis of 30 c is implemented, so when junction temperature drops below 130 c, the device restarts by initiating the soft-start sequence again. soft startup sip12108 deploys an internally regulated soft-start sequence to realize a monotonic startup ramp without any output overshoot. once av in is above uvlo level (2.55 v typ.). both the reference and v out will ramp up slowly to regulation in 1 ms (typ.) with the reference going from 0 v to 0.6 v and v out rising monotonically to the programmed output voltage. during soft-start period, ocp is activated. ovp and short-circuit protection are not active until soft-start is complete. i load ocp threshold i inductor gh skipped gh pulse
sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 12 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pre-bias startup in case of pre-bias startup, output is monitored through v fb pin. if the sensed voltage on v fb is higher than the internal reference ramp value, control logic prevents hs and ls fet from switching to avoid negative output voltage spike and excessive current sinking through ls fet. power good (pgood) sip12108s power good is an open-drain output. pull pgood pin high up to 5 v through a 10k resistor to use this signal. power good window is shown in the below diagram. if voltage level on v fb pin is out of this window, pgood signal is de-asserted by pulling down to gnd. fig. 24 - pgood window and timing diagram design procedure the design process of the sip12108 is quite straight forward. only few passive components such as output capacitors, inductor and r on resistor need to be selected. the following paragr aph describes the selection procedure for these peripheral components for a given operating conditions. in the next example the fo llowing definitions apply: v inmax. : the highest specified input voltage v inmin. : the minimum effective input voltage subject to voltage drops due to connectors, fuses, switches, and pcb traces there are two values of load current to evaluate - continuous load current and peak load current. continuous load current relates to thermal stress considerations which drive the selection of the inductor and input capacitors. peak load current determine s instantaneous component stresses and filtering requir ements such as inductor saturation, output ca pacitors, and design of the current limit circuit. the following specifications are used in this design: ?v in = 3.3 v 10 % ?v out = 1.2 v 1 % ?f sw = 1 mhz ? load = 5 a maximum setting the output voltage the output voltage is set by us ing a resistor divider on the feedback (v fb ) pin. the v fb pin is the negative input of the internal error amplifier. when in regulation the v fb voltage is 0.6 v. the output voltage v o is set based on the following formula. v o = v fb (1 + r1/r2) where r1 and r2 are shown in figure 21. setting switching frequency selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and outp ut capacitor) and the power conversion efficiency. the desired switching frequency, 1 mhz was chosen based on op timizing efficiency while maintaining a small footprint and minimizing component cost. in order to set the design fo r 1 mhz switching frequency, (r on ) resistor which determine s the on-time (indirectly setting the frequency) needs to be calculated using the following equation. vref (0.6 v) v fb vfb_rising_vth_ov (typ. = 0.725 v) vfb_falling_vth_ov (typ. = 0.675 v) vfb_falling_vth_uv (typ. = 0.525 v) vfb_rising_vth_uv (typ. = 0.575 v) pgood pull-high pull-low r on 1 f sw x k ---------------------- 1 1 x 10 6 x 10.45 x 10 -12 -------------------------------------------------------------- - 105 k ? ? ==
sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 13 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 inductor selection in order to determine the indu ctance, the ripple current must first be defined. cost, pcb size , output ripple, and efficiency are all used in the selection process. low inductor values result in smaller size and allo w faster transient performance but create higher ripple current which can reduce efficiency. higher inductor values will re duce the ripple current while compromising the efficiency (higher dcr) and transient response. the ripple current will also se t the boundary for power-save operation. the switcher will typically enter power-save mode when the load current de creases to 1/2 of the ripple current. for example, if ripple current is 1 a then power-save operation will typically start at loads approaching 0.5 a. alternatively, if rippl e current is set at 40 % of maximum load current, then power- save will start for loads less than ~ 20 % of maximum current. inductor selection for the si p12108 should be designed where the ripple current is ~ 50 % in all situations with v in 3.6 v and less. for example 3.3 v in to 1.2 v out at 1 mhz. ? di = v/l x dt = ((3.3 - 1.2)/0.33) x 0.36 = 2.3 a, %di = 2.3/5 = 46 %. for higher v in > 3.6 v ripple current should be set to less then 40 %. for 5 v in to 1.2 v out at 1 mhz di = ((5 - 1.2)/0.68) x 0.36) = 2 a, %di = 2/5 = 40 %. output capacitance calculation the output capacitance is usually chosen to meet transient requirements. a worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capacitance. if the load release is instantaneou s (load changes from maximum to zero in < 1/f sw s), the output capacitor must absorb all the inductors stored energy. this will approximately cause a peak voltage on the capacitor according to the following equation. assuming a peak voltage v peak of 1.3 v (100 mv rise upon load release), and a 5 a load release, the required capacitance is shown by the next equation. if the load release is relatively slow, the output capacitance can be reduced. using mlcc ce ramic capacitors we will use 5 x 22 f or 110 f as the total output capacitance. ? ? ? stability considerations using the output capacitance as a starting point for compensation values. then, taking bode plots and transient response measurements we can fine tune the compensation values. setting the crossover frequenc y to 1/5 of the switching frequency: ? f 0 = f sw /5 = 1 mhz/5 = 200 khz ? setting the compensation zero at 1/5 to 1/10 the crossover frequency for the phase boost: setting c c = 0.47 nf and solve for r c switching frequency variations the switching frequency variat ion in cot can be mainly attributed to the increase in conduction losses as the load increases. the on time is ideally constant so the controller must account for losses by re ducing the off time which increases the overall duty cycle. hence the f sw will tend to increase with load. in power save mode (psm) the ic will run in pulse skip mode at light loads. as the load increases the f sw will increase until it reaches the nominal set f sw . this transition occurs approximately when the load reaches to 20 % of the full load current. design consideration for v out higher then uvlo (2.55 v typ) and/or very slow v in slew rates. the ic ma y have difficulty in starting-up because v in level is limiting how fast v out can rise. in these situations a divider for en pin threshold (~1.15 v) derived from v in can be used. allowing a higher v in level before switching begins and a smooth start-up. for example r top = 60k and r bot = 25k when v in =4 v, en level will be 1.18 v. thermal design the 16 pin package includes a thermal pad for much better thermal performance wh en incorporated in the pcb footprint. as shown in the pcb layout at the end of this document. there are four vias evenly placed on the pad that help transfer the heat to othe r layers. tying the paddle to the bottom layer through vias will provide the best thermal performance. c outmin. l x i out + 1 2 -- - x i ripplemax. ?? ?? v peak ?? 2 - v out ?? 2 ------------------------------------------------------------------------- = 2 c outmin. = 1 h x (5 a + 0.5 x (0.81 a)) 2 (1.3 v) 2 - (1.2 v) 2 = 116.8 f f z = 1 2 x r c x c c = f 0 5 r c = 5 2 x c c x f 0 = 5 2 x 0.47 nf x 200k = 8.469k
sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 14 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 25 - reference board schematic

vin ron fb lx pgood comp avin mode vo vognd vognd vognd r1 100k c3 22uf j2 vo 1 j6 pgood 1 c8* 0.1uf c2 22uf c6 0.1uf r7 2k55 j7 en 1 r5 6k04 j3 vo_gnd 1 u1 sip12107/8 vin1 1 avin 2 en 3 ron 4 lx2 12 lx3 11 vo 10 fb 9 vin2 16 pgnd2 15 pgnd1 14 lx1 13 auto 5 pgood 6 comp 7 agnd 8 agnd-pad 17 r6 5k11 r4 100k j4 vin_gnd 1 r8 1 c5 0.1uf r2 100k c1 0.1uf j1 vin 1 l1 0.47uh r3 100k c4 22uf j5 mode 1 c7 470pf
sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 15 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 bill of materials item qty. reference value voltage pcb footprint part number manufacturer 1 2 c1, c5 0.1 f 50 v c0402-tdk vj0402y104mxqcw1bc vishay 2 2 c2, c3, c4 22 f 10 v c0805-tdk lmk212bj226mg-t murata 4 1 c6 0.1 f 10 v c0603-tdk grm188r71c104ka01d murata 5 1 c7 470 pf 50 v c0402-tdk vj0402a471jxacw1bc tdk 61 c8 (1) dnp - c0603-tdk - - 7 1 j1 vin - tp30 5002k-nd keystone 8 1 j2 vo - tp30 5002k-nd keystone 9 1 j3 vo_gnd - tp30 5002k-nd keystone 10 1 j4 vin_gnd - tp30 5002k-nd keystone 11 1 j5 mode - tp30 5002k-nd keystone 12 1 j6 pgood - tp30 5002k-nd keystone 13 1 j7 en - tp30 5002k-nd keystone 14 1 l1 0.47 h - ihlp1616 ihlp1616bzerr47m11 vishay 15 4 r1, r2, r3, r4 100k 50 v r0402-vishay crcw0402100kfked vishay 16 1 r5 6k04 50 v r0402-vishay tnpw04026k04betd? vishay 17 1 r6 5k11 50 v r0402-vishay crcw04025k11fked vishay 18 1 r7 2k55 50 v r0402-vishay tnpw04022k55betd? vishay 19 1 r8 1 50 v r0402-vishay rc0402fr-071rl yageo 20 1 u1 sip12107, sip12108 - mlp33-16 sip1210x vishay
sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 16 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pcb layout of reference board fig. 26 - top layer fig. 27 - bottom layer
sip12108, sip12108a www.vishay.com vishay siliconix s13-2257-rev. b, 11-nov-13 17 document number: 62699 for technical questions, contact: analogswitchtechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 mlp33-16l case outline notes (1) use millimeters as the primary measurement. (2) dimensioning and to lerances conform to asme y14.5m. - 1994. (3) n is the number of terminal s. nd and ne is the number of terminals in each d and e site respectively. (4) dimensions b applies to plated terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. (5) the pin 1 identifier must be existed on the top surface of the package by using identification mark or other feature of package body. (6) package warpage max. 0.05 mm. ? vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62699 . millimeters (1) inches dimension min. nom. max. min. nom. max. a 0.75 0.85 0.95 0.029 0.033 0.037 a1 0 - 0.05 0 - 0.002 a3 0.20 ref 0.001 ref b 0.18 0.25 0.30 0.007 0.010 0.012 d 3.00 bsc 0.118 bsc d2 1.5 1.6 1.7 0.059 0.063 0.067 e 0.50 bsc 0.020 bsc e 3.00 bsc 0.118 bsc e2 1.5 1.6 1.7 0.059 0.063 0.067 l 0.3 0.4 0.5 0.012 0.016 0.020 n (3) 16 16 nd (3) 44 ne (3) 44 (5) (4)
legal disclaimer notice www.vishay.com vishay revision: 13-jun-16 1 document number: 91000 disclaimer ? all product, product specifications and data ar e subject to change with out notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of th e products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product , (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all implied warranties, includ ing warranties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain types of applicatio ns are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular applic ation. it is the customers responsibility to validate tha t a particular product with the prope rties described in the product sp ecification is suitable for use in a particular application. parameters provided in datasheets and / or specifications may vary in different ap plications and perfor mance may vary over time. all operating parameters, including ty pical parameters, must be va lidated for each customer application by the customer s technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product could result in personal injury or death. customers using or selling vishay product s not expressly indicated for use in such applications do so at their own risk. please contact authorized vishay personnel to obtain writ ten terms and conditions rega rding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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